1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a method of forming a transistor with a critical dimension less than the minimum resolvable feature size of conventional photolithography exposure equipment device.
2. Description of the Relevant Art
An integrated circuit includes a large number of transistors formed within a monolithic semiconductor substrate. Isolation structures such as field oxides or shallow trench dielectrics are used to electrically isolate individual transistors which are thereafter selectively coupled to other transistors through a series of interconnects and contacts to achieve a desired function. The operating characteristics of a transistor fabricated with metal-oxide-semiconductor (MOS) integrated circuit techniques are a function of the transistor's dimensions. In particular, the drain current (I.sub.ds) is proportional to the ratio of the transistor's channel width (W) to the transistor's channel length (L) over a wide range of operating conditions. For a given transistor width and a given biasing condition (e.g., V.sub.G =3V, V.sub.D =3V, and V.sub.s =0V), I.sub.ds is maximized by minimizing the channel length L. Minimizing channel length also improves the speed of integrated circuits comprised of a large number of individual transistors because the larger drain currents characteristic of short channel devices can quickly drive the adjoining transistors into saturation. Minimizing L is, therefore, desirable from a device operation standpoint. In addition, minimizing the transistor length L is desirable because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. Moreover, smaller transistors result in smaller die sizes. Smaller die sizes are desirable from a manufacturing perspective because they increase the number of devices that can be fabricated on a single silicon wafer and decrease the probability that any individual die is rendered inoperable during the fabrication process by randomly occurring defects that are caused by contaminating particles present in every fabrication facility.
The main limitation on minimum feature size in most semiconductor processes is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist layer. The patterned mask transmits the illumination source radiation onto selected areas of the photoresist layer to reproduce the mask pattern in the photoresist layer. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system because the diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleighs criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criteria is satisfied when the 2d =0.61.lambda./NA. Where 2d is the separation distance of two images, .lambda. is the wavelength of the energy source, and NA is the numerical aperture of the lens. It is seen that, for a given lens, the minimum feature size varies directly with wavelength of illumination source.
Commercially available optical photolithography machines are typically equipped with mercury vapor lamps as the illumination source. The characteristic energy spectrum of a mercury vapor lamp contains several distinct peaks in the 300 nm to 450 nm wavelength range. These peaks are commonly referred to by their industry designations. The peak associated with a wavelength of .about.450 nm is designated the "G-line," the .about.405 nm peak the "H-line," and the .about.365 nm peak the "I-line." Photolithography aligners are similarly designated such that it is common to speak of "G-line aligners" and "I-line aligners." The minimum feature size resolvable by an I-line aligner is smaller than the minimum feature size resolvable by a G-line aligner because of the shorter I-line wavelength. "Deep UV" optical aligners utilize energy having wavelengths of .about.248 nm and .about.193 nm to achieve still better resolution than is achievable with I-line aligners.
As process technologies approach and surpass the conventional limits of optical aligners, semiconductor manufacturers are forced to implement alternative techniques to achieve adequate resolution of the minimum features. Unfortunately, the alternatives typically involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. Many wafer fabrication facilities, for example, have extensive capital investment in I-line and deep UV aligners, which are capable of resolving features down to a minimum dimension of approximately 0.3 to 0.4 microns. To achieve adequate resolution of even smaller features, it is typically necessary to abandon the optical alignment equipment entirely and replace it with advanced lithography equipment including e-beam or x-ray lithography. The enormous cost associated with upgrading or replacing optical alignment photolithography equipment can be prohibitive. In addition to the capital required to purchase and install the improved equipment, there are extensive additional costs associated with qualifying the new equipment for production worthiness and training production and maintenance personnel in the operation and care of the new equipment. Therefore, it is highly desirable to implement a manufacturing process that can extend the useful life of existing photolithography equipment by permitting the reproducible fabrication of transistors having critical dimensions that are smaller than the minimum resolvable feature of the photolithography equipment.